#ifndef FPGA_DEFINE_H_INCLUDED
#define FPGA_DEFINE_H_INCLUDED

///////////////Fpga类中用到的宏定义//////////////////
////////////////Moniter寄存器地址///////////////////
#define FPGA_Temp 0
#define FPGA_Vccint 1
#define FPGA_Vccaux 2

#define FPGA_Temp_Max 0x20
#define FPGA_Vccint_Max 0x21
#define FPGA_Vccaux_Max 0x22

#define FPGA_Temp_Min 0x24
#define FPGA_Vccint_Min 0x25
#define FPGA_Vccaux_Min 0x26
/////////////////////////////////////////////////
//cmd方向：_IO()初始化/置0，_IOR()读取，_IOW()写入/置1
//cmd幻数：自己定义
#define MAGICNUM	13
//cmd基数
#define FPGA_NR		0
#define	CG_NR		1
#define ADC_NR		2
#define GPK_NR		3
#define GPM_NR		4
#define GPO_NR		5
#define GPP_NR		6
#define GPQ_NR		7
#define GPA_NR      8
#define GPB_NR      9//0411
#define GPC_NR		45
#define GPD_NR		46
#define GPE_NR		47
#define GPF_NR		48
#define GPG_NR		49
#define GPH_NR		50
#define GPI_NR		51
#define GPJ_NR		52
#define GPL_NR		53
#define GPN_NR		54

#define IO_DIR_A      10
#define IO_DIR_B      11
#define IO_DIR_C      12
#define IO_DIR_D      14
#define IO_DIR_E      15
#define IO_DIR_F      16
#define IO_DIR_G      17
#define IO_DIR_H      18
#define IO_DIR_I      27
#define IO_DIR_J      28
#define IO_DIR_K      29
#define IO_DIR_L      30
#define IO_DIR_M      31
#define IO_DIR_N      32
#define IO_DIR_O      33
#define IO_DIR_P      34
#define IO_DIR_Q      35

#define IO_GET_A      19
#define IO_GET_B      20
#define IO_GET_C      21
#define IO_GET_D      22
#define IO_GET_E      23
#define IO_GET_F      24
#define IO_GET_G      25
#define IO_GET_H      26
#define IO_GET_I      36
#define IO_GET_J      37
#define IO_GET_K      38
#define IO_GET_L      39
#define IO_GET_M      40
#define IO_GET_N      41
#define IO_GET_O      42
#define IO_GET_P      43
#define IO_GET_Q      44


#define U32 unsigned int
#define DEVFILE "/dev/fpga"
#define FPGA_SZ 0x00100000//FPGA内存空间2^20
#define FPGA_RST()		ioctl(fd, _IO(MAGICNUM,FPGA_NR), 0)

#define RST_High()		ioctl(fd, _IOW(MAGICNUM,GPP_NR,int), 14)
#define CFG_DIN_High() 	ioctl(fd, _IOW(MAGICNUM,GPK_NR,int), 10)
#define CFG_PROB_High() ioctl(fd, _IOW(MAGICNUM,GPK_NR,int), 12)
#define CFG_CCLK_High() ioctl(fd, _IOW(MAGICNUM,GPK_NR,int), 13)
#define CFG_CS_High() 	ioctl(fd, _IOW(MAGICNUM,GPK_NR,int), 14)
#define RST_Low()		ioctl(fd, _IO(MAGICNUM,GPP_NR), 14)
#define CFG_DIN_Low() 	ioctl(fd, _IO(MAGICNUM,GPK_NR), 10)
#define CFG_PROB_Low()	ioctl(fd, _IO(MAGICNUM,GPK_NR), 12)
#define CFG_CCLK_Low()	ioctl(fd, _IO(MAGICNUM,GPK_NR), 13)
#define CFG_CS_Low()	ioctl(fd, _IO(MAGICNUM,GPK_NR), 14)

#define SHOW_RST()	ioctl(fd, _IOR(MAGICNUM,GPP_NR,int), 14)
#define CFG_DIN()	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 10)
#define CFG_PROB() 	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 12)
#define CFG_CCLK()	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 13)
#define CFG_CS()	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 14)
#define CFG_DOUT() 	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 9)
#define CFG_DONE() 	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 11)
#define CFG_INIT() 	ioctl(fd, _IOR(MAGICNUM,GPK_NR,int), 15)

#endif // FPGA_DEFINE_H_INCLUDED

